Convolutional Neural Networks (CNNs) have achieved remarkable performance across a wide range of artificial intelligence applications, but their increasing computational demands have placed significant pressure on conventional electronic hardware. The large number of matrix operations and data movements required by CNNs results in high energy consumption and increasing hardware complexity. Although specialized accelerators such as Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs) have enabled the rapid development of modern AI systems, electronic architectures remain constrained by factors such as power dissipation, clock frequency and limitations in transistor scaling.
Photonic computing has emerged as a promising alternative by exploiting the inherent parallelism and high bandwidth of optical systems to perform computationally intensive operations more efficiently. In particular, Photonic Convolutional Neural Networks (PCNNs) can perform convolution operations directly in the optical domain, offering the potential for scalable and energy-efficient AI hardware. However, the practical implementation of PCNNs is affected by hardware non-idealities that can degrade computational accuracy and inference performance.
This research investigates the impact of hardware non-idealities on the performance of Photonic Convolutional Neural Networks under realistic operating conditions. A simulation framework was developed to evaluate the effects of quantization and noise on convolution quality and inference accuracy, with particular emphasis on how different kernel properties influence the robustness of the system. The work also investigates the trade-offs between quantization resolution, classification accuracy and energy efficiency, demonstrating the potential of low-bit operation to reduce Digital-to-Analog Converter (DAC) power consumption while maintaining comparable performance. Additionally, strategies are explored to exploit unused computational resources within the photonic architecture, enabling the generation of additional feature maps without increasing hardware complexity.
Overall, this research contributes to a better understanding of the practical limitations and opportunities of photonic neural network accelerators, providing insights into the design of scalable, robust and energy-efficient hardware architectures for future AI systems.
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